1. Field of the Invention
The present invention relates to a semiconductor device such as an ECL (emitter coupled logic) circuit and a burn-in method thereof. Here, the burn-in implies an activation of a circuit prior to an actual operation in order to stabilize the circuit characteristics and to find a defective circuit at the initial stage thereof.
2. Description of the Prior Art
The circuit configuration and function of the ECL circuit will be described first, that is an example for which a conventional burn-in method has been applied and the burn-in method of the present invention will be applied.
FIG. 16 shows an example of the ECL circuit. In this ECL circuit provided with an OR/NOR gate for three inputs A, B and C, when any one of the three inputs A, B and C becomes high beyond a reference potential V.sub.ref1 (determined as a circuit threshold value), only one transistor (whose input is high) of three transistors Q7.sub.a, Q7.sub.b and Q7.sub.c is turned on and the remaining other transistors and a transistor Q6 are all turned off, so that a current I.sub.CS of a constant current source 60 flows through only one current path (the turned-on transistor) of three current paths P1, P2 and P3. Therefore, a potential at a node NZ becomes higher than that at a node /NZ, so that an output Z of the ECL circuit changes to an "H" (High) level by an emitter follower output stage composed of a transistor Q5.sub.a and a resistor R.sub.a2, and another output /Z of the ECL circuit changes to an "L" (Low) level by another emitter follower output stage composed of a transistor Q5.sub.b and a resistor R.sub.b2.
On the other hand, when all the three inputs A, B and C are low below the reference potential V.sub.ref1, the transistors Q7.sub.a, Q7.sub.b and Q7.sub.c, are turned off and the transistor Q6 is turned on, so that the current I.sub.CS of the constant current source 60 flows through the current path P4. Therefore, a potential at the node NZ becomes lower than that at the node /NZ, so that the output Z of the ECL circuit changes to the "L" level by the above-mentioned emitter follower output stage, and the other output /Z of the ECL circuit changes to the "H" level by the other emitter follower output stage. As described above, a logical sum (=A+B+C) of three inputs A, B and C can be outputted from the output Z of the ECL circuit, and a NOT logical sum (=/(A+B+C)) of three inputs A, B and C can be outputted from the output /Z of the ECL circuit. Further, in the above-mentioned ECL circuit, the reference potential V.sub.ref1 is set to an intermediate level (e.g., V.sub.IM1 =(V.sub.IH1 +V.sub.IL1)/2) between the "H" level (e.g., V.sub.IH1 =-0.8 V) of the input signals A, B and C and the "L" level (e.g., V.sub.IL1 =-1.4 V) thereof, as shown in FIG. 17.
Further, FIG. 18 shows another example of the ECL circuit. This ECL circuit is a two-input multiplexer for passing any one of two inputs A and B through an output Z on the basis of a select signal S. This ECL circuit requires two reference potentials V.sub.ref1 and V.sub.ref2. FIG. 19 shows the relationship among the two reference potentials V.sub.ref1 and V.sub.ref2 and two "H" levels (V.sub.IH1, V.sub.IH2) and two "L" levels (V.sub.IL1, V.sub.IL2) of two input signals A and B. In more detail, the reference potential V.sub.ref1 is an intermediate level between V.sub.IH1 and V.sub.IL1 and the reference potential V.sub.ref2 is an intermediate level between V.sub.IH2 and V.sub.IL2, respectively. Here, V.sub.IH2 =V.sub.IH1 -.PHI. and V.sub.IL2 =V.sub.IL1 -.PHI., respectively, where-.PHI. a V.sub.BE of is equal to a base-emitter voltage bipolar transistor/ (0.8 V, in general).
FIG. 20 shows a bathtub-like curve which represents the change in failure rate of the ECL circuit with the lapse of time. In this bathtub-like characteristic curve, the failure rate can be classified into three periods of initial failure period, accidental failure period and wear-out failure period with the lapse of time. In the initial failure period, the failure due to a design miss or process defects existing in the circuit potentially is actualized at the start of use of the circuit. In the accidental failure period, various failures of the composing elements (which are not actualized in the initial failure period) are actualized in combination at roughly a constant failure rate. In the wear-out failure period, the failure rate due to aged composing elements rises with the lapse of time.
In order to reduce the defective product rate below a constant specified level after the products have been shipped, it is necessary for the maker to stabilize the failure rate at a low level. This process is referred to as a burn-in process. In the case of the burn-in process of the integrated circuit in general, non-defective chips classified according to functions are sealed into packages, and further activated by inputting various test patterns which can realize various actual circuit operation as much as possible so that the failure factors related to the initial defectiveness can be actualized. In the cases of the ECL circuits as shown in FIGS. 16 and 18, for instance, the input signals (test patterns) are switched so that current can be passed through the respective current paths P1, P2, P3 and P4, respectively, in order that the defectiveness factors potentially existing in the respective current paths can be actualized.
A conventional burn-in method will be described herein below with reference to FIG. 16. The four test patterns shown in Table 1 will be applied to the input terminals A, B and C for the burn-in process to make currents pass through the respective current paths P1, P2, P3 and P4 of the OR gate for three inputs of the ECL circuit shown in FIG. 16.
TABLE 1 ______________________________________ POTENTIAL OF TERMINAL A B C CURRENT PATH ______________________________________ H L L P1 L H L P2 L L H P3 L L L P4 ______________________________________
However, in the case of the integrated circuit (IC) device in which a plurality of ECL circuits are connected to each other, extensive and bulky test patterns must be inputted to the device via a large number of input terminals to make currents pass through all of the circuit elements of the device.
For example, in the case of the circuit shown in FIG. 21 which is composed by connecting two of the OR gates of FIG. 16 in series, six test patterns as shown in TABLE 2 must be inputted to the input terminals A1, B1 and C1 of the first OR gate OR1 and the terminals B2 and C2 of the second OR gate for burn-in process.
TABLE 2 ______________________________________ CURRENT POTENTIAL OF TERMINAL PATH A1 B1 C1 B2 C2 OR1 OR2 ______________________________________ H L L L L P1 P1 L H L L L P2 P1 L L H L L P3 P1 L L L H L P4 P2 L L L L H P4 P3 L L L L L P4 P4 ______________________________________
A recent general-scale integrated circuit (LSI) device in general is provided with hundreds of input terminals. The number of test patterns for the burn-in process to the LSI device is in the range of thousands and ten thousands steps and the time required for the process per chip of the LSI device is in the range of several hours and tens of hours.
Since hundreds of chips are generally arranged on a wafer, when it takes one hour for the burn-in process per hip, it will take about a thousand hours (about 42 days) per wafer and this is unpractical.
For that reason, conventionally, after each chip is sealed into a package, a large number of packages are mounted on a burn-in board and simultaneously brought into under the burn-in process.
In the conventional burn-in method described above, however, there exist the following problems: (1) As described above, after each chip is sealed into a package, the burn-in process is performed because it takes time to perform the process to a wafer. Since the sealing of the chips into packages is relatively costly, when the chips are determined to be defective in the burn-in process, the package cost becomes wasteful. This will be the cause of a big problem because ECL circuits are mostly sealed into expensive packages for aiming at high performance. (2) Various burn-in boards must be prepared according to each product or each package. (3) Since various test patterns must be inputted to a large number of input terminals, relatively expensive pulse generators are required in the burn-in process. (4) Extensive and bulky test patterns must be inputted into all of circuits elements of a chip in order to pass current there through and to check the defective factors. Relatively longer hours are thus required for the burn-in process.
The above-mentioned problems have become serious more and more with the recent advance of the diversification of the chip (package), the increasing number of the pins, the decreasing delivery lead time, etc.